System-on-a-chip or system on chip (also known by the acronyms SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). An integrated circuit or monolithic integrated circuit (also referred to as IC, chip, and microchip) is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate. A typical application is in the area of embedded systems.
In current System on Chip, the different components are interconnected by an on-chip interconnect. An interconnect can basically be construed as a bus for circuitry. Examples of such interconnect are Open Core Protocol (also known by the acronym OCP) or Advanced RISC Machines®'s (also known by the acronym ARM) Advanced eXtensible Interface (also known by the acronym AXI). The components may be Control Processor Units (also known by the acronym CPU). ARM A9 processor core is an example of CPU. Direct memory access (also known by the acronym DMA) engines or peripherals such as Universal Asynchronous Receivers Transmitters (also known by the acronym UARTs) may also be considered as components.
Each component is usually memory mapped. Furthermore, the components exchange transactions between each other.
Such transactions comprise a request sent to another component, wherein this request is executed. As illustrations, the request may be an instruction to read, to write or to fetch from memory. The component that sends the request is a transactions initiator component or initiator component whereas the component that executes the request is a transactions target component or target component. Some components are capable of being both a transactions initiator and a transactions target, while others may be only be a transaction initiator or a transaction target.
Each transaction that is initiated shall have a response that contains either the information requested or status of the original request. As examples, the information requested may be read data while the status may be successful or failed write indications. The response is sent by the target component to the component which initiated the transaction.
In addition to transactions that are sent on the on-chip bus, components also exchange status information such as interrupts. As interrupts are usually side-band signals, on-chip interconnects therefore also contain side-band signals.
Sometimes, all the functionalities needed in a SoC cannot be implemented efficiently in a single die. In such cases, the SoC is split into multiple, usually two. For instance, some components contain analog modules that are designed in a different technology process node while other components are purely digital and can be designed in a smaller process node.
Low Latency Interface (also known by the acronym LLI) may be used to enable such flexible partitioning of a SoC or a system into multiple physical dies while the software implemented in the system considers them as a single logical die. The LLI is standardized in Mobile Industry Processor Interface (also known by the acronym MIPI). LLI is a point to point interface that allows two dies to communicate as if the other die was located on the die considered. LLI is a bi-directional interface made up of dual-simplex sub-links. LLI allows both dies to initiate and to receive transactions simultaneously. In other words, LLI can be thought of as a “bus-extension” or “interconnect tunnel”. Through special transactions called “Service transactions”, LLI can carry the side-band signals such as interrupts.
In order to efficiently manage the LLI physical link power supply, it is possible to power down the link or put the link into very low power supply states. The physical link requires time to be active when starting from a low power supply state. Such time is usually in the range of milliseconds. As “interconnect tunnel” protocols such as LLI should be able to ensure the low latency while transporting the transactions, it is desirable that all outstanding transactions are completed before the link is put in such low power consumption states or in the extreme case, powered down.